Signal Integrity/EMC Pro Tune Up 4 2010

(1 Day including hands on SI, EMI, and PI simulation labs)

To Register for this class Click here ( Tuition is listed on Registration Page) North American Class Schedule Click here

Pro Tune Up 4 is a Signal Integrity and Electromagnetic Compliance “how to do it right” class that gives students a well rounded explanation of proper high speed system design.  The single day class is based on a design methodology developed by a major telecommunications company which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time.    “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests….on the first try!

Target Audience: Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems that will work reliably at full speed and still remain quiet enough to pass regulatory EMI tests.  The basic methodology upon which this class is based was documented to achieve repeatable first pass success as a standard practice.

Content
Basic Signal Integrity including board layer stack-up specification, high speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.

Power Delivery is a lot more than one 0.1uF and five 0.01uF caps per pin.  Power delivery depends upon stack-up, capacitor selection, placement, mounting technique, and quantity.  Typical target impedance for memory systems must be around 0.1 ohm from DC to the highest frequency of interest.  The highest frequency of interest is most likely in the microwave region.  Poor design can result in power delivery impedance poles and inter plane resonances.  Many of the mysterious SI and EMI issues can be traced directly to poor power delivery design.

Root causes and cures for EMI.  The class’s primary approach is to stop the noise at the source.  If noise is eliminated at the source, you do not need to chase it around the board.  The recent proliferation of ASIC’s from hell has prompted us to add a section on shielding and filtering.  If the problem is in the device, not the board, and you can not find a better behaved substitute for that device, your only choice is to shield and filter. 

Single Ended Bus Issues    If you have a memory or address bus with both high and low speed devices, do the high speed devices belong close to the processor with the low speed devices farther away, or vice versa?  How do you terminate?  What about option slots?

How LVDS really works.  With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme.  However there can be other complications like Cross Talk and EMI if you do it incorrectly.
 
Giga Bit Serial / SERDES interface routing issues …PCI Express  We explain what is important and also debunk some of the popular myths about routing these types of interfaces.

The Analog / Digital Interface i.e. Isolation vs. Communication

To Moat or Not to Moat  Understanding the issues related to “quiet grounds.”

Connectors, Board to Board SI, EMI, and Power Issues

Chip Level Package Issues and how to defend against them.

Basic Shielding Theory as it applies to Switching Power Supplies

Critical elements in an effective high speed system design process.  Simply performing a solid pre-layout design review and including the correct personnel can raise you first time odds of success at least 50%.  Implementing a full process can result in first time success 99% of the time.

Teaching Method ... Explain, Demonstrate, Do
           
The instructor will explain the problem and an appropriate method to solve that problem.
The instructor will demonstrate the solution using industry standard software tools.
The students will do the work for themselves using lab computers and sample problems.

The students perform computer based labs to help lock in understanding of the physics behind classical high speed design problems.  This also gives them the freedom to try their own examples.  Simply hearing information results in about a 30% retention rate.  Seeing a demonstration will raise the retention rate closer 50%.  If you actually do the work on something meaningful to the student, the retention is over 80%.

The purpose of this class is not to impress anyone with complex formulae and higher math.  There are perfectly good simulators to do the heavy lifting.  The purpose is to give layout designers and EE’s the tools to make their next design a quiet, reliable, full speed system on the first try.

 Location & Tuition for Pro Tune Up 4

PTU4 is offered through out North America as a public 1 day class which includes hands on labs using standard industrial simulations tools.  Assuming registration 10 days in advance of class and payment 5 days in advance of the class, tuition is $695.  Late registration / payment is $795.  The schedule of classes is on:
www.SIEMC.com/class_schedule.htm

Private On Site Pro Tune Up 4 Classes

PTU4 is also offered as an onsite company private class for $6500.  This covers the tuition for up to 10 students.  The price includes the instructor’s T&L expenses and the computers used for the labs.  Client is responsible for the meeting room, projector, and student lunches. Consulting days can be appended to PTU4 training in order to expand on the class material or to jump start a new project.  Consulting days coincident with the class are $3,000 per day including T&L.

To Register for this class Click here ( Tuition is listed on Registration Page)

Why should I attend this class?
Any Electrical Engineer, CAD Layout Designer, or Technical Manager who is tired of playing "Whack A Mole"** would find this class extremely useful. Students who have implemented this methodology have regularly produced complex designs that do indeed work correctly on the first implementation.  On average, that saves about $12000 and two months (calendar time) on the average system using 2007 technology.   Any financially responsible manager will agree that saving two design turns on the typical system results in huge savings and potentially even larger profits by getting to market earlier.

**For those of you who have not attended one of my previous classes, "Whack a Mole" is an arcade game that kids love. There are nine holes and a worm like creature ...a mole ...sticks its head up and the kids whack it with a plastic sledge hammer. After a few seconds the "mole" pops up in another location. The faster the kids whack the mole, the faster it moves to a new location. Kids love the game, but from a high speed design standpoint, it becomes an infuriating game quite rapidly. This class will help you permanently end the SI / EMI version of the "Whack A Mole" game.

Tuition:  $795 per student.  For early registration 10 days in advance of the class and payment settled 5 days in advance of the class we offer a special rate of $695.

Viewing the SIEMC JumpStart 3.0 pre-class homework video is a required prerequisite for attending the class. I need to be assure that everyone is at a common starting point for terminology, etc. You can skip the last chapter of the book which explains the in class agenda for the JumpStart 3 class.

Down load full fidelity 1024 x 769 quality video & telephone quality audio version of SIEMC JumpStart V3 Pre-Class Homework. Down load the30 Mb file, unZIP it into any directory and click the big "purple ball" to open the video book and view the table of contents

Use this link to get a PDF description of this class-->Printable PDF Version of this class description